There are three existing sampling methods for UWB pulse signals: direct sampling, frequency-domain sampling, and order-less sampling. For direct sampling, because the input signal bandwidth of each ADC is very large, it can make the ADC's sample-and-hold circuit difficult to design. The sampling result of the ADC is greatly affected by the sampling clock jitter, so the sampling clock must reach a higher accuracy. At the same time, When the higher equivalent sampling rate is achieved, more ADCs are needed and the resource overhead is large. In addition, when the UWB system is subject to narrow-band signal interference, it is necessary to increase the time to alternate the dynamic range of the ADC to ensure receiver performance. Frequency domain sampling is less sensitive to clock jitter than direct sampling. However, the filter bank design is complicated. Sequential undersampling is achieved with two reference clock oscillators. Assuming f0 = 9.999 000 MHz and f0 + Δf = 10 MHz, the time required to sequentially under-sample and reconstruct a pulse signal is 1 ms and the equivalent sample rate achievable is 99.99 GHz. The gap between its requirements is: the signal reconstruction time is long, susceptible to clock jitter.